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SN74LVC16374AGQLR

1.65V~3.6V 150MHz 16 Bit D-Type Flip Flop BOTTOM 74LVC16374 56 Pins 20μA 74LVC Series 56-VFBGA

Manufacturer: Texas Instruments
Origchip NO: 815-SN74LVC16374AGQLR
Package: 56-VFBGA
Datasheet: PDF
Stock: 839
Description: 1.65V~3.6V 150MHz 16 Bit D-Type Flip Flop BOTTOM 74LVC16374 56 Pins 20μA 74LVC Series 56-VFBGA(Kg)

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Details

Tags

Parameters
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	56-VFBGA
Number of Pins	56
Weight	58.796911mg
Operating Temperature	-40°C~85°C TA
Packaging	Cut Tape (CT)
Series	74LVC
Pbfree Code	no
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	56
Type	D-Type
Subcategory	FF/Latches
Packing Method	TAPE AND REEL
Technology	CMOS
Voltage - Supply	1.65V~3.6V
Terminal Position	BOTTOM
Terminal Form	BALL
Supply Voltage	1.8V
Terminal Pitch	0.65mm
Base Part Number	74LVC16374
Function	Standard
Output Type	Tri-State, Non-Inverted
Number of Elements	2
Polarity	Non-Inverting
Load Capacitance	50pF
Number of Ports	2
Number of Bits	16
Clock Frequency	150MHz
Propagation Delay	4.9 ns
Turn On Delay Time	1.5 ns
Family	LVC/LCX/Z
Logic Function	D-Type, Flip-Flop
Current - Quiescent (Iq)	20μA
Current - Output High, Low	24mA 24mA
Number of Bits per Element	8
Max Propagation Delay @ V, Max CL	4.5ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup	4.5 ns
Trigger Type	Positive Edge
Input Capacitance	5pF
Number of Input Lines	3
Number of Output Lines	1
Clock Edge Trigger Type	Positive Edge
Length	7mm
Width	4.5mm
Radiation Hardening	No
RoHS Status	ROHS3 Compliant
Lead Free	Contains Lead

SN74LVC16374AGQLR Overview

In the form of 56-VFBGA, it has been packaged. The Cut Tape (CT)package contains it. T flip flop uses Tri-State, Non-Invertedas the output. It is configured with a trigger that uses a value of Positive Edge. Surface Mountmounts this electrical part. A 1.65V~3.6Vsupply voltage is required for it to operate. The operating temperature is -40°C~85°C TA. There is D-Type type of electronic flip flop associated with this device. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. It should not exceed 150MHzin terms of its output frequency. D latch consists of 2 elements. T flip flop consumes 20μA quiescent energy. Terminations are 56. Members of the 74LVC16374family make up this object. Power is provided by a 1.8V supply. This T flip flop has a capacitance of 5pF farads at the input. In this case, the D flip flop belongs to the LVC/LCX/Zfamily. This electronic part is mounted in the way of Surface Mount. Basically, it is designed with a set of 56 pins. There is a clock edge trigger type of Positive Edgeon this device. It is included in FF/Latches. There are 16bits in this flip flop. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TAPE AND REEL. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The JK flip flop is with 1 output lines to operate. It is reported that there are 3 input lines.