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SN74LVC112APWR

1.65V~3.6V 150MHz JK Type Flip Flop DUAL 74LVC112 16 Pins 10μA 74LVC Series 16-TSSOP (0.173, 4.40mm Width)

Manufacturer: Texas Instruments
Origchip NO: 815-SN74LVC112APWR
Package: 16-TSSOP (0.173, 4.40mm Width)
Datasheet: -
Stock: 139
Description: 1.65V~3.6V 150MHz JK Type Flip Flop DUAL 74LVC112 16 Pins 10μA 74LVC Series 16-TSSOP (0.173, 4.40mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time	6 Weeks
Lifecycle Status	ACTIVE (Last Updated: 4 days ago)
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	16-TSSOP (0.173, 4.40mm Width)
Number of Pins	16
Weight	61.887009mg
Operating Temperature	-40°C~85°C TA
Packaging	Tape & Reel (TR)
Series	74LVC
JESD-609 Code	e4
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	16
ECCN Code	EAR99
Type	JK Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latches
Packing Method	TR
Technology	CMOS
Voltage - Supply	1.65V~3.6V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	1.8V
Base Part Number	74LVC112
Function	Set(Preset) and Reset
Output Type	Differential
Polarity	Non-Inverting
Supply Voltage-Min (Vsup)	2V
Number of Circuits	2
Load Capacitance	50pF
Output Current	24mA
Clock Frequency	150MHz
Propagation Delay	7.1 ns
Turn On Delay Time	1 ns
Family	LVC/LCX/Z
Logic Function	AND, Flip-Flop, JK-Type
Current - Quiescent (Iq)	10μA
Current - Output High, Low	24mA 24mA
Number of Bits per Element	1
Max Propagation Delay @ V, Max CL	5.9ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup	4.8 ns
Trigger Type	Negative Edge
Input Capacitance	4.5pF
Schmitt Trigger	No
Number of Input Lines	3
Clock Edge Trigger Type	Negative Edge
Height	1.2mm
Length	5mm
Width	4.4mm
Thickness	1mm
Radiation Hardening	No
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

SN74LVC112APWR Overview

The item is packaged in 16-TSSOP (0.173, 4.40mm Width)cases. There is an embedded version in the package Tape & Reel (TR). In the configuration, Differentialis used as the output. It is configured with a trigger that uses Negative Edge. The electronic part is mounted in the way of Surface Mount. A supply voltage of 1.65V~3.6V is required for operation. It is operating at a temperature of -40°C~85°C TA. This logic flip flop is classified as type JK Type. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. It should not exceed 150MHzin terms of its output frequency. This process consumes 10μA quiescents. There have been 16 terminations. The 74LVC112 family contains it. It is powered from a supply voltage of 1.8V. Its input capacitance is 4.5pFfarads. This D flip flop belongs to the family of LVC/LCX/Z. In this case, the electronic component is mounted in the way of Surface Mount. It is designed with 16 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Negative Edge. This part is included in FF/Latches. For normal operation, the supply voltage (Vsup) should be kept above 2V. Its flexibility is enhanced by 2 circuits. As a result of its reliable performance, this T flip flop is suitable for TR. With a current output of 24mA , it offers maximum design flexibility. Currently, there are 3 lines of input.