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SN74LV574ADW

2V~5.5V 175MHz 8 Bit D-Type Flip Flop DUAL 74LV574 20 Pins 20μA 74LV Series 20-SOIC (0.295, 7.50mm Width)

Manufacturer: Texas Instruments
Origchip NO: 815-SN74LV574ADW
Package: 20-SOIC (0.295, 7.50mm Width)
Datasheet: PDF
Stock: 708
Description: 2V~5.5V 175MHz 8 Bit D-Type Flip Flop DUAL 74LV574 20 Pins 20μA 74LV Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time	6 Weeks
Lifecycle Status	ACTIVE (Last Updated: 2 days ago)
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	20-SOIC (0.295, 7.50mm Width)
Number of Pins	20
Weight	500.709277mg
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	74LV
JESD-609 Code	e4
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	20
ECCN Code	EAR99
Type	D-Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latches
Technology	CMOS
Voltage - Supply	2V~5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	2.5V
Base Part Number	74LV574
Function	Standard
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Polarity	Non-Inverting
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	2V
Number of Channels	8
Load Capacitance	50pF
Number of Ports	2
Output Current	16mA
Number of Bits	8
Clock Frequency	175MHz
Propagation Delay	19.6 ns
Turn On Delay Time	4.8 ns
Family	LV/LV-A/LVX/H
Logic Function	D-Type, Flip-Flop
Current - Quiescent (Iq)	20μA
Current - Output High, Low	16mA 16mA
Max Propagation Delay @ V, Max CL	10.6ns @ 5V, 50pF
Trigger Type	Positive Edge
Input Capacitance	1.8pF
Power Supply Current-Max (ICC)	0.02mA
Number of Input Lines	3
Count Direction	UNIDIRECTIONAL
Clock Edge Trigger Type	Positive Edge
Translation	N/A
Max Frequency@Nom-Sup	45000000Hz
Height	2.65mm
Length	12.8mm
Width	7.5mm
Thickness	2.35mm
Radiation Hardening	No
REACH SVHC	No SVHC
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

SN74LV574ADW Overview

In the form of 20-SOIC (0.295, 7.50mm Width), it has been packaged. It is included in the package Tube. T flip flop uses Tri-State, Non-Invertedas its output configuration. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. Powered by a 2V~5.5Vvolt supply, it operates as follows. In the operating environment, the temperature is -40°C~85°C TA. This D latch has the type D-Type. FPGAs belonging to the 74LVseries contain this type of chip. Its output frequency should not exceed 175MHz Hz. The element count is 1 . It consumes 20μA of quiescent A total of 20 terminations have been made. JK flip flop belongs to 74LV574 family. A voltage of 2.5V is used to power it. A JK flip flop with a 1.8pFfarad input capacitance is used here. It is a member of the LV/LV-A/LVX/Hfamily of D flip flop. There is an electronic component mounted in the way of Surface Mount. There are 20pins on it. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is included in FF/Latches. Flip flops designed with 8bits are used in this part. There is a 5.5Vmaximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be kept above 2V. There are 2 ports embedded in the flip flops. The output current of 16mA makes it feature maximum design flexibility. It is reported that there are 3 input lines. A total of 8 channels are available.