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SN74LS112AN

4.75V~5.25V 45MHz JK Type Flip Flop DUAL 74LS112 16 Pins 6mA 74LS Series 16-DIP (0.300, 7.62mm)

Manufacturer: Texas Instruments
Origchip NO: 815-SN74LS112AN
Package: 16-DIP (0.300, 7.62mm)
Datasheet: -
Stock: 790
Description: 4.75V~5.25V 45MHz JK Type Flip Flop DUAL 74LS112 16 Pins 6mA 74LS Series 16-DIP (0.300, 7.62mm)(Kg)

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Details

Tags

Parameters
Factory Lead Time	6 Weeks
Lifecycle Status	ACTIVE (Last Updated: 3 days ago)
Mount	Through Hole
Mounting Type	Through Hole
Package / Case	16-DIP (0.300, 7.62mm)
Number of Pins	16
Weight	951.693491mg
Operating Temperature	0°C~70°C TA
Packaging	Tube
Series	74LS
JESD-609 Code	e4
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	16
ECCN Code	EAR99
Type	JK Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latches
Technology	TTL
Voltage - Supply	4.75V~5.25V
Terminal Position	DUAL
Supply Voltage	5V
Base Part Number	74LS112
Function	Set(Preset) and Reset
Output Type	Differential
Operating Supply Voltage	5V
Polarity	Non-Inverting
Power Supplies	5V
Number of Channels	2
Operating Supply Current	100μA
Nominal Supply Current	100μA
Output Current	8mA
Clock Frequency	45MHz
Propagation Delay	20 ns
Turn On Delay Time	15 ns
Family	LS
Logic Function	AND, Flip-Flop, JK-Type
Current - Quiescent (Iq)	6mA
Current - Output High, Low	400μA 8mA
Max I(ol)	0.008 A
Number of Bits per Element	1
Max Propagation Delay @ V, Max CL	20ns @ 5V, 15pF
Trigger Type	Negative Edge
Schmitt Trigger	No
Power Supply Current-Max (ICC)	6mA
Number of Input Lines	5
Clock Edge Trigger Type	Negative Edge
Max Frequency@Nom-Sup	30000000Hz
Height	5.08mm
Length	19.3mm
Width	6.35mm
Thickness	3.9mm
Radiation Hardening	No
REACH SVHC	No SVHC
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

SN74LS112AN Overview

16-DIP (0.300, 7.62mm)is the packaging method. There is an embedded version in the package Tube. In the configuration, Differentialis used as the output. Negative Edgeis the trigger it is configured with. Through Holeis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 4.75V~5.25V volts. Currently, the operating temperature is 0°C~70°C TA. JK Typeis the type of this D latch. The 74LSseries comprises this type of FPGA. This D flip flop should not have a frequency greater than 45MHz. This process consumes 6mA quiescents. A total of 16terminations have been recorded. This D latch belongs to the family of 74LS112. A voltage of 5V is used as the power supply for this D latch. An electronic device belonging to the family LScan be found here. The electronic part is mounted in the way of Through Hole. The 16pins are designed into the board. Its clock edge trigger type is Negative Edge. The part is included in FF/Latches. The D latch runs on a voltage of 5V volts. The supply voltage should be maintained at 5V for high efficiency. With an output current of 8mA, it is possible to design the device in any way you want. Currently, there are 5 lines of input. It is reported that there are 2 channels.