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SN74LS107AD

4.75V~5.25V 45MHz JK Type Flip Flop DUAL 74LS107 14 Pins 6mA 74LS Series 14-SOIC (0.154, 3.90mm Width)

Manufacturer: Texas Instruments
Origchip NO: 815-SN74LS107AD
Package: 14-SOIC (0.154, 3.90mm Width)
Datasheet: -
Stock: 797
Description: 4.75V~5.25V 45MHz JK Type Flip Flop DUAL 74LS107 14 Pins 6mA 74LS Series 14-SOIC (0.154, 3.90mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time	6 Weeks
Lifecycle Status	ACTIVE (Last Updated: 3 days ago)
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	14-SOIC (0.154, 3.90mm Width)
Number of Pins	14
Weight	129.387224mg
Operating Temperature	0°C~70°C TA
Packaging	Tube
Series	74LS
JESD-609 Code	e4
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	14
ECCN Code	EAR99
Type	JK Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latches
Technology	TTL
Voltage - Supply	4.75V~5.25V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Base Part Number	74LS107
Function	Reset
Output Type	Differential
Operating Supply Voltage	5V
Polarity	Non-Inverting
Power Supplies	5V
Number of Channels	2
Output Current	8mA
Clock Frequency	45MHz
Propagation Delay	20 ns
Turn On Delay Time	15 ns
Family	LS
Logic Function	Flip-Flop, JK-Type
Current - Quiescent (Iq)	6mA
Current - Output High, Low	400μA 8mA
Max I(ol)	0.008 A
Number of Bits per Element	1
Max Propagation Delay @ V, Max CL	20ns @ 5V, 15pF
Trigger Type	Negative Edge
Schmitt Trigger	No
Power Supply Current-Max (ICC)	6mA
Number of Input Lines	4
fmax-Min	30 MHz
Clock Edge Trigger Type	Negative Edge
Max Frequency@Nom-Sup	30000000Hz
Height	1.75mm
Length	8.65mm
Width	3.91mm
Thickness	1.58mm
Radiation Hardening	No
REACH SVHC	No SVHC
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

SN74LS107AD Overview

It is embeded in 14-SOIC (0.154, 3.90mm Width) case. D flip flop is included in the Tubepackage. There is a Differentialoutput configured with it. It is configured with a trigger that uses a value of Negative Edge. There is an electronic component mounted in the way of Surface Mount. A supply voltage of 4.75V~5.25V is required for operation. A temperature of 0°C~70°C TAis used in the operation. JK Typeis the type of this D latch. The FPGA belongs to the 74LS series. In order for it to function properly, its output frequency should not exceed 45MHz. There is a consumption of 6mAof quiescent energy. Terminations are 14. This D latch belongs to the family of 74LS107. A voltage of 5V provides power to the D latch. It is a member of the LSfamily of D flip flop. Surface Mount mounts this electronic component. This board has 14 pins. This device exhibits a clock edge trigger type of Negative Edge. It is included in FF/Latches. The system runs on a power supply of 5V watts. In order to achieve high efficiency, the supply voltage should be maintained at 5V. As a result of its output current of 8mA, it is very flexible in terms of design. Currently, there are 4 input lines present. Currently, there are 2 channels available.