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SN74F112DR

4.5V~5.5V 130MHz JK Type Flip Flop DUAL 74F112 16 Pins 19mA 74F Series 16-SOIC (0.154, 3.90mm Width)

Manufacturer: Texas Instruments
Origchip NO: 815-SN74F112DR
Package: 16-SOIC (0.154, 3.90mm Width)
Datasheet: PDF
Stock: 231
Description: 4.5V~5.5V 130MHz JK Type Flip Flop DUAL 74F112 16 Pins 19mA 74F Series 16-SOIC (0.154, 3.90mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time	6 Weeks
Lifecycle Status	ACTIVE (Last Updated: 3 days ago)
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	16-SOIC (0.154, 3.90mm Width)
Number of Pins	16
Weight	141.690917mg
Operating Temperature	0°C~70°C TA
Packaging	Tape & Reel (TR)
Series	74F
JESD-609 Code	e4
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	16
ECCN Code	EAR99
Type	JK Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latch
Packing Method	TR
Technology	TTL
Voltage - Supply	4.5V~5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Base Part Number	74F112
Function	Set(Preset) and Reset
Qualification Status	Not Qualified
Output Type	Differential
Operating Supply Voltage	5V
Polarity	Non-Inverting
Power Supplies	5V
Number of Circuits	2
Load Capacitance	50pF
Output Current	20mA
Clock Frequency	130MHz
Propagation Delay	6.5 ns
Turn On Delay Time	4.6 ns
Family	F/FAST
Logic Function	AND, Flip-Flop, JK-Type
Current - Quiescent (Iq)	19mA
Current - Output High, Low	1mA 20mA
Number of Bits per Element	1
Max Propagation Delay @ V, Max CL	6.5ns @ 5V, 50pF
Prop. Delay@Nom-Sup	7.5 ns
Trigger Type	Negative Edge
Schmitt Trigger	No
Clock Edge Trigger Type	Negative Edge
Height	1.75mm
Length	9.9mm
Width	3.91mm
Thickness	1.58mm
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

SN74F112DR Overview

The package is in the form of 16-SOIC (0.154, 3.90mm Width). There is an embedded version in the package Tape & Reel (TR). T flip flop is configured with an output of Differential. This trigger is configured to use Negative Edge. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 4.5V~5.5V. Currently, the operating temperature is 0°C~70°C TA. JK Typedescribes this flip flop. JK flip flop belongs to the 74Fseries of FPGAs. There should be no greater frequency than 130MHzon its output. It consumes 19mA of quiescent current without being affected by external factors. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74F112 family contains this object. The power source is powered by 5V. This D flip flop belongs to the family of F/FAST. A part of the electronic system is mounted in the way of Surface Mount. There are 16pins on it. This device has the clock edge trigger type of Negative Edge. This device is part of the FF/Latchbase part number family. In order to achieve its superior flexibility, 2 circuits are used. As a result of its reliable performance, this T flip flop is suitable for TR. The system runs on a power supply of 5V watts. For high efficiency, the supply voltage should be set to 5V. It offers maximum design flexibility with its output current of 20mA.