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MM74HCT574N

4.5V~5.5V 33MHz D-Type Flip Flop DUAL 8μA 74HCT Series 20-DIP (0.300, 7.62mm)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-MM74HCT574N
Package: 20-DIP (0.300, 7.62mm)
Datasheet: PDF
Stock: 389
Description: 4.5V~5.5V 33MHz D-Type Flip Flop DUAL 8μA 74HCT Series 20-DIP (0.300, 7.62mm)(Kg)

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Details

Tags

Parameters
Mounting Type	Through Hole
Package / Case	20-DIP (0.300, 7.62mm)
Surface Mount	NO
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	74HCT
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	3 (168 Hours)
Number of Terminations	20
Type	D-Type
Terminal Finish	MATTE TIN
Additional Feature	BROADSIDE VERSION OF 374
Technology	CMOS
Voltage - Supply	4.5V~5.5V
Terminal Position	DUAL
Peak Reflow Temperature (Cel)	NOT APPLICABLE
Supply Voltage	5V
Terminal Pitch	2.54mm
Time@Peak Reflow Temperature-Max (s)	NOT APPLICABLE
JESD-30 Code	R-PDIP-T20
Function	Standard
Qualification Status	Not Qualified
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	4.5V
Number of Ports	2
Clock Frequency	33MHz
Family	HCT
Current - Quiescent (Iq)	8μA
Output Characteristics	3-STATE
Current - Output High, Low	7.2mA 7.2mA
Output Polarity	TRUE
Number of Bits per Element	8
Max Propagation Delay @ V, Max CL	30ns @ 5V, 50pF
Trigger Type	Positive Edge
Input Capacitance	10pF
Length	26.075mm
Width	7.62mm
RoHS Status	ROHS3 Compliant

MM74HCT574N Overview

20-DIP (0.300, 7.62mm)is the way it is packaged. There is an embedded version in the package Tube. This output is configured with Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. There is an electrical part that is mounted in the way of Through Hole. A voltage of 4.5V~5.5Vis required for its operation. It is operating at -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. JK flip flop is a part of the 74HCTseries of FPGAs. There should be no greater frequency than 33MHzon its output. A total of 1elements are present in it. As a result, it consumes 8μA quiescent current. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. An input voltage of 5Vpowers the D latch. JK flip flop input capacitance is 10pF farads. HCTis the family of this D flip flop. It reaches the maximum supply voltage (Vsup) at 5.5V. It is imperative that the supply voltage (Vsup) is maintained above 4.5Vin order to ensure normal operation. A D flip flop with 2embedded ports is available. In addition, you can refer to the additinal BROADSIDE VERSION OF 374 of the D latch.