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MC10EP35DTR2G

-3V~-5.5V 3GHz 2 Bit JK Type Flip Flop DUAL 50mA 10EP Series 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-MC10EP35DTR2G
Package: 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)
Datasheet: PDF
Stock: 489
Description: -3V~-5.5V 3GHz 2 Bit JK Type Flip Flop DUAL 50mA 10EP Series 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	8-TSSOP, 8-MSOP (0.118, 3.00mm Width)
Surface Mount	YES
Operating Temperature	-40°C~85°C TA
Packaging	Tape & Reel (TR)
Series	10EP
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	3 (168 Hours)
Number of Terminations	8
Type	JK Type
Terminal Finish	MATTE TIN
Additional Feature	NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
Technology	ECL
Voltage - Supply	-3V~-5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	3.3V
Terminal Pitch	0.65mm
Time@Peak Reflow Temperature-Max (s)	40
JESD-30 Code	S-PDSO-G8
Function	Reset
Qualification Status	COMMERCIAL
Output Type	Differential
Number of Elements	1
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	3V
Number of Bits	2
Clock Frequency	3GHz
Family	10E
Current - Quiescent (Iq)	50mA
Output Polarity	COMPLEMENTARY
Trigger Type	Positive Edge
Propagation Delay (tpd)	0.49 ns
Length	3mm
Width	3mm
RoHS Status	ROHS3 Compliant

MC10EP35DTR2G Overview

The package is in the form of 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). There is an embedded version in the package Tape & Reel (TR). T flip flop uses Differentialas its output configuration. In the configuration of the trigger, Positive Edgeis used. It is mounted in the way of Surface Mount. It operates with a supply voltage of -3V~-5.5V. It is operating at -40°C~85°C TA. This D latch has the type JK Type. JK flip flop is a part of the 10EPseries of FPGAs. A frequency of 3GHzshould not be exceeded by its output. In total, it contains 1 elements. There is a consumption of 50mAof quiescent energy. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. An input voltage of 3.3Vpowers the D latch. Devices in the 10Efamily are electronic devices. There are 2bits in this flip flop. As soon as 5.5Vis reached, Vsup reaches its maximum value. A normal operating voltage (Vsup) should remain above 3V. In addition, NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5Vis a characteristic of it.