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MC100EP52MNR4G

-3V~-5.5V 3GHz 1 Bit D-Type Flip Flop DUAL 100EP52 8 Pins 45mA 100EP Series 8-VFDFN Exposed Pad

Manufacturer: ON Semiconductor
Origchip NO: 598-MC100EP52MNR4G
Package: 8-VFDFN Exposed Pad
Datasheet: PDF
Stock: 136
Description: -3V~-5.5V 3GHz 1 Bit D-Type Flip Flop DUAL 100EP52 8 Pins 45mA 100EP Series 8-VFDFN Exposed Pad(Kg)

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Details

Tags

Parameters
Factory Lead Time	7 Weeks
Lifecycle Status	ACTIVE (Last Updated: 1 day ago)
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	8-VFDFN Exposed Pad
Number of Pins	8
Operating Temperature	-40°C~85°C TA
Packaging	Tape & Reel (TR)
Published	2000
Series	100EP
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	8
Type	D-Type
Terminal Finish	Nickel/Gold/Palladium (Ni/Au/Pd)
Additional Feature	NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
Subcategory	FF/Latches
Packing Method	TAPE AND REEL
Technology	ECL
Voltage - Supply	-3V~-5.5V
Terminal Position	DUAL
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	260
Supply Voltage	3.3V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	40
Base Part Number	100EP52
Function	Standard
Qualification Status	Not Qualified
Output Type	Differential
Polarity	Non-Inverting
Supply Voltage-Max (Vsup)	5.5V
Power Supplies	-4.5V
Supply Voltage-Min (Vsup)	3V
Number of Circuits	1
Output Current	50mA
Number of Bits	1
Clock Frequency	3GHz
Propagation Delay	380 ps
Turn On Delay Time	330 ps
Current - Quiescent (Iq)	45mA
Halogen Free	Halogen Free
Trigger Type	Positive, Negative
High Level Output Current	-50mA
Low Level Output Current	50mA
Power Supply Current-Max (ICC)	47mA
Clock Edge Trigger Type	Positive Edge
Max Frequency@Nom-Sup	4000000000Hz
Length	2mm
Width	2mm
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

MC100EP52MNR4G Overview

It is packaged in the way of 8-VFDFN Exposed Pad. Package Tape & Reel (TR)embeds it. Differentialis the output configured for it. It is configured with a trigger that uses a value of Positive, Negative. Surface Mountmounts this electrical part. The JK flip flop operates at a voltage of -3V~-5.5V. It is at -40°C~85°C TAdegrees Celsius that the system is operating. A flip flop of this type is classified as a D-Type. In FPGA terms, D flip flop is a type of 100EPseries FPGA. You should not exceed 3GHzin the output frequency of the device. There is 45mA quiescent consumption. A total of 8 terminations have been made. The 100EP52 family contains it. The D flip flop is powered by a voltage of 3.3V . A part of the electronic system is mounted in the way of Surface Mount. As you can see from the design, it has pins with 8. Its clock edge trigger type is Positive Edge. This device has the base part number FF/Latches. This flip flop is designed with 1 Bits. In this case, the maximum supply voltage (Vsup) reaches 5.5V. For normal operation, the supply voltage (Vsup) should be kept above 3V. 1 circuits are used to achieve its superior flexibility. Considering its reliability, this T flip flop is well suited for TAPE AND REEL. It operates from -4.5V power supplies. With a current output of 50mA , it offers maximum design flexibility. As an additional reference, you may refer to electronic flip flop NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V. A -50mAis set for the high level output current. In the low level output current setting, 50mAis used.