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MC100EL30DW

4.2V~5.7V 1.2GHz D-Type Flip Flop DUAL 100EL Series 20-SOIC (0.295, 7.50mm Width)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-MC100EL30DW
Package: 20-SOIC (0.295, 7.50mm Width)
Datasheet: PDF
Stock: 157
Description: 4.2V~5.7V 1.2GHz D-Type Flip Flop DUAL 100EL Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Shipping Cost

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The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

Shipping Method

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Delivery Time

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FedEx International, 5-7 business days.

The following are some common countries' logistic time.
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Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	20-SOIC (0.295, 7.50mm Width)
Surface Mount	YES
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	100EL
JESD-609 Code	e0
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	3 (168 Hours)
Number of Terminations	20
Type	D-Type
Terminal Finish	TIN LEAD
Additional Feature	NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
Technology	ECL
Voltage - Supply	4.2V~5.7V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	240
Supply Voltage	5V
Time@Peak Reflow Temperature-Max (s)	30
JESD-30 Code	R-PDSO-G20
Function	Set(Preset) and Reset
Qualification Status	COMMERCIAL
Output Type	Differential
Number of Elements	3
Supply Voltage-Max (Vsup)	5.7V
Supply Voltage-Min (Vsup)	4.2V
Clock Frequency	1.2GHz
Output Characteristics	OPEN-EMITTER
Output Polarity	COMPLEMENTARY
Number of Bits per Element	1
Trigger Type	Positive Edge
Propagation Delay (tpd)	0.82 ns
Height Seated (Max)	2.65mm
Width	7.5mm
RoHS Status	Non-RoHS Compliant

MC100EL30DW Overview

The item is packaged in 20-SOIC (0.295, 7.50mm Width)cases. D flip flop is embedded in the Tube package. Currently, the output is configured to use Differential. The trigger it is configured with uses Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A voltage of 4.2V~5.7Vis used as the supply voltage. In the operating environment, the temperature is -40°C~85°C TA. It belongs to the type D-Typeof flip flops. This type of FPGA is a part of the 100EL series. There should be no greater frequency than 1.2GHzon its output. D latch consists of 3 elements. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. A voltage of 5V provides power to the D latch. Vsup reaches its maximum value at 5.7V. For normal operation, the supply voltage (Vsup) should be above 4.2V. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V.