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74VCX16722MTD

1.2V~3.6V 250MHz D-Type Flip Flop DUAL 20μA 74VCX Series 64-TFSOP (0.240, 6.10mm Width)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-74VCX16722MTD
Package: 64-TFSOP (0.240, 6.10mm Width)
Datasheet: PDF
Stock: 840
Description: 1.2V~3.6V 250MHz D-Type Flip Flop DUAL 20μA 74VCX Series 64-TFSOP (0.240, 6.10mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	64-TFSOP (0.240, 6.10mm Width)
Surface Mount	YES
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	74VCX
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	2 (1 Year)
Number of Terminations	64
Type	D-Type
Terminal Finish	MATTE TIN
Technology	CMOS
Voltage - Supply	1.2V~3.6V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	1.8V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
JESD-30 Code	R-PDSO-G64
Function	Standard
Qualification Status	COMMERCIAL
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Supply Voltage-Max (Vsup)	3.6V
Number of Ports	2
Clock Frequency	250MHz
Family	ALVC/VCX/A
Current - Quiescent (Iq)	20μA
Output Characteristics	3-STATE
Current - Output High, Low	24mA 24mA
Output Polarity	TRUE
Number of Bits per Element	22
Max Propagation Delay @ V, Max CL	3.6ns @ 3.3V, 30pF
Trigger Type	Positive Edge
Input Capacitance	3.5pF
Propagation Delay (tpd)	9.2 ns
RoHS Status	ROHS3 Compliant

74VCX16722MTD Overview

As a result, it is packaged as 64-TFSOP (0.240, 6.10mm Width). As part of the package Tube, it is embedded. As configured, the output uses Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. There is an electric part mounted in the way of Surface Mount. Powered by a 1.2V~3.6Vvolt supply, it operates as follows. The operating temperature is -40°C~85°C TA. The type of this D latch is D-Type. FPGAs belonging to the 74VCXseries contain this type of chip. In order for it to function properly, its output frequency should not exceed 250MHz. D latch consists of 1 elements. As a result, it consumes 20μA quiescent current and is not affected by external forces. Currently, there are 64 terminations. An input voltage of 1.8Vpowers the D latch. The input capacitance of this JK flip flopis 3.5pF farads. The electronic device belongs to the ALVC/VCX/Afamily. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.