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74LVC16374ADGG,112

1.65V~3.6V 300MHz 16 Bit D-Type Flip Flop DUAL 74LVC16374 48 Pins 20μA 74LVC Series 48-TFSOP (0.240, 6.10mm Width)

Manufacturer: Nexperia USA Inc.
Origchip NO: 554-74LVC16374ADGG,112
Package: 48-TFSOP (0.240, 6.10mm Width)
Datasheet: PDF
Stock: 451
Description: 1.65V~3.6V 300MHz 16 Bit D-Type Flip Flop DUAL 74LVC16374 48 Pins 20μA 74LVC Series 48-TFSOP (0.240, 6.10mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time	8 Weeks
Contact Plating	Gold
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	48-TFSOP (0.240, 6.10mm Width)
Number of Pins	48
Operating Temperature	-40°C~125°C TA
Packaging	Tube
Published	2010
Series	74LVC
JESD-609 Code	e4
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	48
Type	D-Type
Technology	CMOS
Voltage - Supply	1.65V~3.6V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	2.7V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	30
Base Part Number	74LVC16374
Function	Standard
Output Type	Tri-State, Non-Inverted
Number of Elements	2
Polarity	Non-Inverting
Supply Voltage-Max (Vsup)	3.6V
Number of Ports	2
Output Current	50mA
Number of Bits	16
Clock Frequency	300MHz
Propagation Delay	7.5 ns
Quiescent Current	100nA
Turn On Delay Time	7 ns
Family	LVC/LCX/Z
Current - Quiescent (Iq)	20μA
Output Characteristics	3-STATE
Current - Output High, Low	24mA 24mA
Number of Bits per Element	8
Max Propagation Delay @ V, Max CL	5.4ns @ 3.3V, 50pF
Trigger Type	Positive Edge
Input Capacitance	5pF
Clock Edge Trigger Type	Positive Edge
Width	6.1mm
Radiation Hardening	No
REACH SVHC	No SVHC
RoHS Status	ROHS3 Compliant

74LVC16374ADGG,112 Overview

48-TFSOP (0.240, 6.10mm Width)is the way it is packaged. You can find it in the Tubepackage. T flip flop uses Tri-State, Non-Invertedas its output configuration. This trigger is configured to use Positive Edge. Surface Mountis in the way of this electric part. The supply voltage is set to 1.65V~3.6V. It is at -40°C~125°C TAdegrees Celsius that the system is operating. It is an electronic flip flop with the type D-Type. JK flip flop is a part of the 74LVCseries of FPGAs. Its output frequency should not exceed 300MHz Hz. The element count is 2 . There is a consumption of 20μAof quiescent energy. Currently, there are 48 terminations. This D latch belongs to the family of 74LVC16374. A voltage of 2.7V provides power to the D latch. Its input capacitance is 5pFfarads. The electronic device belongs to the LVC/LCX/Zfamily. There is an electronic part mounted in the way of Surface Mount. With its 48pins, it is designed to work with most electronic flip flops. This device has the clock edge trigger type of Positive Edge. There are 16bits in this flip flop. As soon as 3.6Vis reached, Vsup reaches its maximum value. The flip flop has 2embedded ports. The 50mA output current allows it to be designed with the greatest amount of flexibility. This D latch consumes 100nA quiescent current at all.