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74LV74D-Q100J

1V~5.5V 110MHz D-Type Flip Flop DUAL 74LV74 14 Pins 74LV Series 14-SOIC (0.154, 3.90mm Width)

Manufacturer: Nexperia USA Inc.
Origchip NO: 554-74LV74D-Q100J
Package: 14-SOIC (0.154, 3.90mm Width)
Datasheet: PDF
Stock: 463
Description: 1V~5.5V 110MHz D-Type Flip Flop DUAL 74LV74 14 Pins 74LV Series 14-SOIC (0.154, 3.90mm Width)(Kg)

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Details

Tags

Parameters
Published	2013
Series	74LV
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	14
Type	D-Type
Technology	CMOS
Voltage - Supply	1V~5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	NOT SPECIFIED
Supply Voltage	3.3V
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Base Part Number	74LV74
Function	Set(Preset) and Reset
Output Type	Differential
Operating Supply Voltage	3.3V
Polarity	Non-Inverting
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	1V
Clock Frequency	110MHz
Propagation Delay	17 ns
Quiescent Current	20μA
Turn On Delay Time	13 ns
Family	LV/LV-A/LVX/H
Logic Function	AND, D-Type, Flip-Flop
Current - Output High, Low	12mA 12mA
Number of Bits per Element	1
Max Propagation Delay @ V, Max CL	17ns @ 5V, 50pF
Trigger Type	Positive Edge
Input Capacitance	3.5pF
Number of Input Lines	2
fmax-Min	56 MHz
Clock Edge Trigger Type	Positive Edge
Length	8.65mm
Width	3.9mm
RoHS Status	ROHS3 Compliant
Factory Lead Time	4 Weeks
Contact Plating	Gold
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	14-SOIC (0.154, 3.90mm Width)
Number of Pins	14
Operating Temperature	-40°C~125°C TA
Packaging	Tape & Reel (TR)

74LV74D-Q100J Overview

The flip flop is packaged in 14-SOIC (0.154, 3.90mm Width). As part of the package Tape & Reel (TR), it is embedded. It is configured with Differentialas an output. JK flip flop uses Positive Edgeas the trigger. Surface Mountis positioned in the way of this electronic part. A supply voltage of 1V~5.5V is required for operation. -40°C~125°C TAis the operating temperature. A flip flop of this type is classified as a D-Type. JK flip flop is a part of the 74LVseries of FPGAs. Its output frequency should not exceed 110MHz. There are 14 terminations,If you search by 74LV74, you will find similar parts. An input voltage of 3.3Vpowers the D latch. Its input capacitance is 3.5pFfarads. LV/LV-A/LVX/His the family of this D flip flop. It is mounted in the way of Surface Mount. It is designed with 14 pins. This device has the clock edge trigger type of Positive Edge. Vsup reaches 5.5V, the maximal supply voltage. A normal operating voltage (Vsup) should remain above 1V. Optimal efficiency requires a supply voltage of 3.3V. The number of input lines is 2. 20μAquiescent current consumed.