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74F374SCX

4.5V~5.5V 140MHz D-Type Flip Flop DUAL 86mA 74F Series 20-SOIC (0.295, 7.50mm Width)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-74F374SCX
Package: 20-SOIC (0.295, 7.50mm Width)
Datasheet: PDF
Stock: 374
Description: 4.5V~5.5V 140MHz D-Type Flip Flop DUAL 86mA 74F Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	20-SOIC (0.295, 7.50mm Width)
Surface Mount	YES
Operating Temperature	0°C~70°C TA
Packaging	Tape & Reel (TR)
Published	2011
Series	74F
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	20
Type	D-Type
Terminal Finish	MATTE TIN
Technology	TTL
Voltage - Supply	4.5V~5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Reach Compliance Code	unknown
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
JESD-30 Code	R-PDSO-G20
Function	Standard
Qualification Status	Not Qualified
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	4.5V
Number of Ports	2
Clock Frequency	140MHz
Family	F/FAST
Current - Quiescent (Iq)	86mA
Output Characteristics	3-STATE
Current - Output High, Low	3mA 24mA
Output Polarity	TRUE
Number of Bits per Element	8
Max Propagation Delay @ V, Max CL	8.5ns @ 5V, 50pF
Trigger Type	Positive Edge
Height Seated (Max)	2.65mm
Width	7.5mm
RoHS Status	ROHS3 Compliant

74F374SCX Overview

As a result, it is packaged as 20-SOIC (0.295, 7.50mm Width). You can find it in the Tape & Reel (TR)package. Tri-State, Non-Invertedis the output configured for it. It is configured with a trigger that uses Positive Edge. There is an electric part mounted in the way of Surface Mount. It operates with a supply voltage of 4.5V~5.5V. It is operating at a temperature of 0°C~70°C TA. D-Typedescribes this flip flop. The 74Fseries comprises this type of FPGA. Its output frequency should not exceed 140MHz Hz. In total, it contains 1 elements. Despite external influences, it consumes 86mAof quiescent current. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. A voltage of 5V is used to power it. In this case, the D flip flop belongs to the F/FASTfamily. Vsup reaches 5.5V, the maximal supply voltage. For normal operation, the supply voltage (Vsup) should be above 4.5V. The D flip flop has no ports embedded.