All Products

View All >>

74AUP2G80GT,115

0.8V~3.6V 309MHz D-Type Flip Flop DUAL 74AUP2G80 500nA 74AUP Series 8-XFDFN

Manufacturer: Nexperia USA Inc.
Origchip NO: 554-74AUP2G80GT,115
Package: 8-XFDFN
Datasheet: PDF
Stock: 178
Description: 0.8V~3.6V 309MHz D-Type Flip Flop DUAL 74AUP2G80 500nA 74AUP Series 8-XFDFN(Kg)

Purchase & Inquiry

Transport

Purchase

You may place an order without registering to XINJIADA.
We strongly suggest you sign in before purchasing as you can track your order in real time.

Means of Payment

For your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and wire transfer.

RFQ (Request for Quotations)

It is recommended to request for quotations to get the latest prices and inventories about the part.
Our sales will reply to your request by email within 24 hours.

IMPORTANT NOTICE

1. You'll receive an order information email in your inbox. (Please remember to check the spam folder if you didn't hear from us).
2. Since inventories and prices may fluctuate to some extent, the sales manager is going to reconfirm the order and let you know if there are any updates.

Shipping Cost

Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.)
The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

Shipping Method

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

Delivery Time

Once the goods are shipped, estimated delivery time depends on the shipping methods you chose:

FedEx International, 5-7 business days.

The following are some common countries' logistic time.
transport

Details

Tags

Parameters
Factory Lead Time	13 Weeks
Mounting Type	Surface Mount
Package / Case	8-XFDFN
Surface Mount	YES
Operating Temperature	-40°C~125°C TA
Packaging	Tape & Reel (TR)
Published	2010
Series	74AUP
JESD-609 Code	e3
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	8
Type	D-Type
Terminal Finish	Tin (Sn)
Technology	CMOS
Voltage - Supply	0.8V~3.6V
Terminal Position	DUAL
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	260
Supply Voltage	1.2V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	30
Base Part Number	74AUP2G80
JESD-30 Code	R-PDSO-N8
Function	Standard
Qualification Status	Not Qualified
Output Type	Inverted
Number of Elements	2
Supply Voltage-Max (Vsup)	3.6V
Supply Voltage-Min (Vsup)	0.8V
Clock Frequency	309MHz
Family	AUP/ULP/V
Current - Quiescent (Iq)	500nA
Current - Output High, Low	4mA 4mA
Output Polarity	TRUE
Number of Bits per Element	1
Max Propagation Delay @ V, Max CL	6.4ns @ 3.3V, 30pF
Trigger Type	Positive Edge
Input Capacitance	0.6pF
Height Seated (Max)	0.5mm
RoHS Status	ROHS3 Compliant

74AUP2G80GT,115 Overview

The item is packaged in 8-XFDFNcases. The package Tape & Reel (TR)contains it. T flip flop uses Invertedas its output configuration. Positive Edgeis the trigger it is configured with. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 0.8V~3.6V volts, it operates. It is at -40°C~125°C TAdegrees Celsius that the system is operating. This logic flip flop is classified as type D-Type. It belongs to the 74AUPseries of FPGAs. Its output frequency should not exceed 309MHz. In total, it contains 2 elements. There is 500nA quiescent consumption. A total of 8terminations have been recorded. D latch belongs to the 74AUP2G80 family. Power is supplied from a voltage of 1.2V volts. JK flip flop input capacitance is 0.6pF farads. It is a member of the AUP/ULP/Vfamily of D flip flop. It reaches the maximum supply voltage (Vsup) at 3.6V. Normal operation requires a supply voltage (Vsup) above 0.8V.