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74AUP1G374GN,132

0.8V~3.6V 309MHz 1 Bit D-Type Flip Flop DUAL 74AUP1G374 6 Pins 74AUP Series 6-XFDFN

Manufacturer: Nexperia USA Inc.
Origchip NO: 554-74AUP1G374GN,132
Package: 6-XFDFN
Datasheet: PDF
Stock: 522
Description: 0.8V~3.6V 309MHz 1 Bit D-Type Flip Flop DUAL 74AUP1G374 6 Pins 74AUP Series 6-XFDFN(Kg)

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Details

Tags

Parameters
Factory Lead Time	13 Weeks
Contact Plating	Tin
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	6-XFDFN
Number of Pins	6
Operating Temperature	-40°C~125°C TA
Packaging	Tape & Reel (TR)
Series	74AUP
JESD-609 Code	e3
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	6
Type	D-Type
Technology	CMOS
Voltage - Supply	0.8V~3.6V
Terminal Position	DUAL
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	NOT SPECIFIED
Supply Voltage	1.1V
Terminal Pitch	0.3mm
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Base Part Number	74AUP1G374
Function	Standard
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Polarity	Non-Inverting
Supply Voltage-Min (Vsup)	0.8V
Number of Bits	1
Clock Frequency	309MHz
Propagation Delay	13.4 ns
Quiescent Current	500nA
Turn On Delay Time	23.6 ns
Family	AUP/ULP/V
Output Characteristics	3-STATE
Current - Output High, Low	4mA 4mA
Max Propagation Delay @ V, Max CL	5.8ns @ 3.3V, 30pF
Trigger Type	Positive Edge
Input Capacitance	0.8pF
Clock Edge Trigger Type	Positive Edge
Height Seated (Max)	0.35mm
Width	0.9mm
RoHS Status	ROHS3 Compliant

74AUP1G374GN,132 Overview

It is embeded in 6-XFDFN case. The package Tape & Reel (TR)contains it. Tri-State, Non-Invertedis the output configured for it. It is configured with a trigger that uses Positive Edge. There is an electric part mounted in the way of Surface Mount. A supply voltage of 0.8V~3.6V is required for operation. It is operating at -40°C~125°C TA. There is D-Type type of electronic flip flop associated with this device. FPGAs belonging to the 74AUPseries contain this type of chip. This D flip flop should not have a frequency greater than 309MHz. A total of 1 elements are present. The number of terminations is 6. Members of the 74AUP1G374family make up this object. An input voltage of 1.1Vpowers the D latch. The input capacitance of this JK flip flopis 0.8pF farads. Electronic devices of this type belong to the AUP/ULP/Vfamily. It is mounted in the way of Surface Mount. The 6pins are designed into the board. This device exhibits a clock edge trigger type of Positive Edge. Flip flops designed with 1bits are used in this part. For normal operation, the supply voltage (Vsup) should be above 0.8V. It consumes 500nA current.