All Products

View All >>

74ACTQ18823MTD

4.5V~5.5V 100MHz D-Type Flip Flop DUAL 80μA 74ACTQ Series 56-TFSOP (0.240, 6.10mm Width)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-74ACTQ18823MTD
Package: 56-TFSOP (0.240, 6.10mm Width)
Datasheet: PDF
Stock: 831
Description: 4.5V~5.5V 100MHz D-Type Flip Flop DUAL 80μA 74ACTQ Series 56-TFSOP (0.240, 6.10mm Width)(Kg)

Purchase & Inquiry

Transport

Purchase

You may place an order without registering to XINJIADA.
We strongly suggest you sign in before purchasing as you can track your order in real time.

Means of Payment

For your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and wire transfer.

RFQ (Request for Quotations)

It is recommended to request for quotations to get the latest prices and inventories about the part.
Our sales will reply to your request by email within 24 hours.

IMPORTANT NOTICE

1. You'll receive an order information email in your inbox. (Please remember to check the spam folder if you didn't hear from us).
2. Since inventories and prices may fluctuate to some extent, the sales manager is going to reconfirm the order and let you know if there are any updates.

Shipping Cost

Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.)
The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

Shipping Method

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

Delivery Time

Once the goods are shipped, estimated delivery time depends on the shipping methods you chose:

FedEx International, 5-7 business days.

The following are some common countries' logistic time.
transport

Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	56-TFSOP (0.240, 6.10mm Width)
Surface Mount	YES
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	74ACTQ
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	2 (1 Year)
Number of Terminations	56
Type	D-Type
Terminal Finish	MATTE TIN
Additional Feature	WITH CLEAR AND CLOCK ENABLE
Technology	CMOS
Voltage - Supply	4.5V~5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Terminal Pitch	0.5mm
Reach Compliance Code	unknown
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
JESD-30 Code	R-PDSO-G56
Function	Reset
Qualification Status	COMMERCIAL
Output Type	Tri-State, Non-Inverted
Number of Elements	2
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	4.5V
Number of Ports	2
Clock Frequency	100MHz
Family	ACT
Current - Quiescent (Iq)	80μA
Output Characteristics	3-STATE
Current - Output High, Low	24mA 24mA
Output Polarity	TRUE
Number of Bits per Element	9
Max Propagation Delay @ V, Max CL	9ns @ 5V, 50pF
Trigger Type	Positive Edge
Input Capacitance	4.5pF
Propagation Delay (tpd)	10 ns
Length	14mm
Width	6.1mm
RoHS Status	ROHS3 Compliant

74ACTQ18823MTD Overview

56-TFSOP (0.240, 6.10mm Width)is the way it is packaged. The Tubepackage contains it. There is a Tri-State, Non-Invertedoutput configured with it. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Surface Mount. With a supply voltage of 4.5V~5.5V volts, it operates. A temperature of -40°C~85°C TAis considered to be the operating temperature. This D latch has the type D-Type. JK flip flop belongs to the 74ACTQseries of FPGAs. A frequency of 100MHzshould not be exceeded by its output. The element count is 2 . There is 80μA quiescent consumption. There are 56 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The D flip flop is powered by a voltage of 5V . A JK flip flop with a 4.5pFfarad input capacitance is used here. A device of this type belongs to the family of ACT. 5.5Vis the maximum supply voltage (Vsup). Normally, the supply voltage (Vsup) should be above 4.5V. There are 2 ports embedded in the flip flops. Additionally, it is characterized by WITH CLEAR AND CLOCK ENABLE.