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74ACT825SC

4.5V~5.5V 158MHz D-Type Flip Flop DUAL 80μA 74ACT Series 24-SOIC (0.295, 7.50mm Width)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-74ACT825SC
Package: 24-SOIC (0.295, 7.50mm Width)
Datasheet: PDF
Stock: 193
Description: 4.5V~5.5V 158MHz D-Type Flip Flop DUAL 80μA 74ACT Series 24-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	24-SOIC (0.295, 7.50mm Width)
Surface Mount	YES
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	74ACT
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	24
Type	D-Type
Terminal Finish	MATTE TIN
Additional Feature	WITH TRIPLE OUTPUT ENABLE
Technology	CMOS
Voltage - Supply	4.5V~5.5V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Reach Compliance Code	unknown
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
JESD-30 Code	R-PDSO-G24
Function	Master Reset
Qualification Status	COMMERCIAL
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Supply Voltage-Max (Vsup)	5.5V
Supply Voltage-Min (Vsup)	4.5V
Number of Ports	2
Clock Frequency	158MHz
Family	ACT
Current - Quiescent (Iq)	80μA
Output Characteristics	3-STATE
Current - Output High, Low	24mA 24mA
Output Polarity	TRUE
Number of Bits per Element	8
Max Propagation Delay @ V, Max CL	9.5ns @ 5V, 50pF
Trigger Type	Positive Edge
Input Capacitance	4.5pF
Height Seated (Max)	2.65mm
Width	7.5mm
RoHS Status	ROHS3 Compliant

74ACT825SC Overview

It is embeded in 24-SOIC (0.295, 7.50mm Width) case. It is contained within the Tubepackage. Currently, the output is configured to use Tri-State, Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. There is an electronic component mounted in the way of Surface Mount. A voltage of 4.5V~5.5Vis used as the supply voltage. Temperature is set to -40°C~85°C TA. D-Typeis the type of this D latch. In terms of FPGAs, it belongs to the 74ACT series. You should not exceed 158MHzin the output frequency of the device. D latch consists of 1 elements. This process consumes 80μA quiescents. There are 24 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. A voltage of 5V is used to power it. The input capacitance of this T flip flop is 4.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. ACTis the family of this D flip flop. There is a 5.5Vmaximum supply voltage (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 4.5V. The D flip flop is embedded with 2ports. It is also characterized by WITH TRIPLE OUTPUT ENABLE.