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74AC574PC

2V~6V 153MHz D-Type Flip Flop DUAL 40μA 74AC Series 20-DIP (0.300, 7.62mm)

Manufacturer: Rochester Electronics, LLC
Origchip NO: 699-74AC574PC
Package: 20-DIP (0.300, 7.62mm)
Datasheet: PDF
Stock: 891
Description: 2V~6V 153MHz D-Type Flip Flop DUAL 40μA 74AC Series 20-DIP (0.300, 7.62mm)(Kg)

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Details

Tags

Parameters
Mounting Type	Through Hole
Package / Case	20-DIP (0.300, 7.62mm)
Surface Mount	NO
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	74AC
JESD-609 Code	e3
Pbfree Code	yes
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	3 (168 Hours)
Number of Terminations	20
Type	D-Type
Terminal Finish	MATTE TIN
Additional Feature	BROADSIDE VERSION OF 374
Technology	CMOS
Voltage - Supply	2V~6V
Terminal Position	DUAL
Peak Reflow Temperature (Cel)	NOT APPLICABLE
Supply Voltage	3.3V
Terminal Pitch	2.54mm
Reach Compliance Code	unknown
Time@Peak Reflow Temperature-Max (s)	NOT APPLICABLE
JESD-30 Code	R-PDIP-T20
Function	Standard
Qualification Status	Not Qualified
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Supply Voltage-Max (Vsup)	6V
Supply Voltage-Min (Vsup)	2V
Number of Ports	2
Clock Frequency	153MHz
Family	AC
Current - Quiescent (Iq)	40μA
Output Characteristics	3-STATE
Current - Output High, Low	24mA 24mA
Output Polarity	TRUE
Number of Bits per Element	8
Max Propagation Delay @ V, Max CL	9.5ns @ 5V, 50pF
Trigger Type	Positive Edge
Input Capacitance	4.5pF
Length	26.075mm
Width	7.62mm
RoHS Status	ROHS3 Compliant

74AC574PC Overview

The package is in the form of 20-DIP (0.300, 7.62mm). It is contained within the Tubepackage. Tri-State, Non-Invertedis the output configured for it. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Through Hole. Powered by a 2V~6Vvolt supply, it operates as follows. It is operating at -40°C~85°C TA. It belongs to the type D-Typeof flip flops. JK flip flop belongs to the 74ACseries of FPGAs. It should not exceed 153MHzin its output frequency. A total of 1elements are present in it. It consumes 40μA of quiescent current without being affected by external factors. Terminations are 20. The power source is powered by 3.3V. A JK flip flop with a 4.5pFfarad input capacitance is used here. It is a member of the ACfamily of D flip flop. As soon as 6Vis reached, Vsup reaches its maximum value. Normally, the supply voltage (Vsup) should be kept above 2V. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. In addition, BROADSIDE VERSION OF 374is a characteristic of it.